Predicting Post-Route PPA from Macro and Standard-Cell Placements (U. of Alberta)

<p>Researchers from University of Alberta published a technical paper titled “PPAPlace: Differentiable Cross-Stage Objectives for Chip Placement Optimization.” Abstract: “Macro placement significantly affects a chip&#8217;s post-route performance, power, and area (PPA). Most placement methods optimize half-perimeter wirelength (HPWL) as the primary objective. However, recent benchmarking shows a near-zero correlation between HPWL and post-route timing metrics... <a class="read_more" href="https://semiengineering.com/predicting-post-route-ppa-from-macro-and-standard-cell-placements-u-of-alberta/">&#187; read more</a></p> <p>The post <a href="https://semiengineering.com/predicting-post-route-ppa-from-macro-and-standard-cell-placements-u-of-alberta/">Predicting Post-Route PPA from Macro and Standard-Cell Placements (U. of Alberta)</a> appeared first on <a href="https://semiengineering.com">Semiconductor Engineering</a>.</p>