HW Information-Flow Tracking for Pre-Silicon Security Testing (Princeton, MIT, EPFL)

<p>Researchers at Princeton University, MIT CSAIL, and EPFL published a technical paper titled “Efficient Hardware Information-Flow Tracking for Pre-Silicon Security Testing.” Abstract “Register-Transfer Level (RTL) simulation is widely used to test hardware before it is fabricated. To allow testing for security related information flow properties, such as confidentiality and integrity, taint logic can be automatically... <a class="read_more" href="https://semiengineering.com/hw-information-flow-tracking-for-pre-silicon-security-testing-princeton-mit-epfl/">&#187; read more</a></p> <p>The post <a href="https://semiengineering.com/hw-information-flow-tracking-for-pre-silicon-security-testing-princeton-mit-epfl/">HW Information-Flow Tracking for Pre-Silicon Security Testing (Princeton, MIT, EPFL)</a> appeared first on <a href="https://semiengineering.com">Semiconductor Engineering</a>.</p>