Chip Industry Technical Paper Roundup: July 28

<p>HW methods to throttle AI; M3D DRAM; interconnect signal-integrity analysis; 3D mask effects in high/hyper-NA EUV litho; compute-in-interconnect and memory; NbAs nanowire interconnects; and 3D conformal thin-film patterning.</p> <p>The post <a href="https://semiengineering.com/chip-industry-technical-paper-roundup-july-28/">Chip Industry Technical Paper Roundup: July 28</a> appeared first on <a href="https://semiengineering.com">Semiconductor Engineering</a>.</p>