DIGITIMES Insight: AI scaling is moving from chip shrinkage to system integration
TSMC said the next phase of AI performance growth will depend less on shrinking a single chip and more on combining multiple chips, memory, and advanced packaging inside larger systems. The shift could reshape semiconductor competition, as demand for compute, bandwidth, power delivery, and cooling rises in tandem. The company outlined the trend at its heterogeneous integration forum during SEMICON Taiwan 2026, saying AI computing transistors in a single CoWoS package are set to rise more than 48-fold by 2029 from 2024 levels, while total HBM bandwidth is expected to increase more than 34-fold.
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