Backside Clock Meshes Cut Skew and Power in 2nm Nanosheets (UCSC)

<p>Researchers at the University of California, Santa Cruz published a technical paper titled “Design Space Exploration of Backside Clock Meshes for 2 nm GAAFET BSPDN Technology.” Abstract Excerpt: “Clock meshes are used in high-performance VLSI designs to minimize skew and tolerate on-chip variation, but they spend scarce routing resources on premium metal layers. Backside power... <a class="read_more" href="https://semiengineering.com/backside-clock-meshes-cut-skew-and-power-in-2nm-nanosheets-ucsc/">&#187; read more</a></p> <p>The post <a href="https://semiengineering.com/backside-clock-meshes-cut-skew-and-power-in-2nm-nanosheets-ucsc/">Backside Clock Meshes Cut Skew and Power in 2nm Nanosheets (UCSC)</a> appeared first on <a href="https://semiengineering.com">Semiconductor Engineering</a>.</p>