Formal Acceleration on FPGA. Innovation in Verification

<p>Extending hardware acceleration to formal verification is a powerful idea to extend hardware acceleration to a verification domain that has not got much attention for acceleration. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and lecturer at Stanford,&#8230; <a href="https://semiwiki.com/eda/371437-formal-acceleration-on-fpga-innovation-in-verification/" class="read-more">Read More </a></p> <p>The post <a href="https://semiwiki.com/eda/371437-formal-acceleration-on-fpga-innovation-in-verification/">Formal Acceleration on FPGA. Innovation in Verification</a> appeared first on <a href="https://semiwiki.com">SemiWiki</a>.</p>